1. Field of the Invention
The present invention relates to a semiconductor memory device, e.g., a static random access memory (SRAM).
2. Description of the Related Art
In recent SRAMs, the scaling of the cell size is advancing with the development of the micropatterning technique, and a read current per memory cell is lowering accordingly. In addition, the variation in cell current amount is increasing due to the increase in memory capacity and processing variations. Consequently, a memory cell having the smallest cell current of all memory cells makes it difficult to increase the operating speed of the SRAM. Under the circumstances, the importance of a method of accurately measuring the cell current of a fabricated memory cell is increasing in order to analyze defects and manage production lines.
On the other hand, an SRAM having a hierarchical bit line structure capable of data read with a small cell current has been developed. The hierarchical bit line structure is a circuit system in which a bit line comprises a local bit line and global bit line. The local bit line is connected to a local sense amplifier and local write driver. The global bit line is connected to a global sense amplifier and global write driver.
More specifically, a plurality of local bit lines whose bit line capacitance is reduced by finely dividing a bit line are connected to a plurality of local sense amplifiers. The local sense amplifier amplifies data and sends the amplified data to the global bit line. The global sense amplifier connected to the global bit line determines the data. That is, cell data is read out by the two stages of bit lines/sense amplifiers. By thus hierarchizing the bit lines, the capacitance of each bit line can be reduced, and this makes it possible to reduce the cell current.
In this hierarchical bit line type SRAM, a method that outputs the cell current to a pad by selecting a local bit line and global bit line by column switches is conventionally used as a method of directly measuring the cell current. In this method, however, a cell current flowing through only the local bit line is output outside via the global bit line and a few column switch stages. Therefore, the parasitic resistances and leakage noise of the global bit line and column switches interfere with accurate cell current measurement.
As a related technique of this kind, a technique that suppresses the increase in chip size by using one cell current monitoring bus is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 10-241400).